As the number of circuit elements to be created on an integrated circuit continually increases and the size of each element correspondingly decreases, each step in the creation of such circuits via photolithographic processing is analyzed to determine sources of possible processing distortions. For example, it is now common practice for circuit designers to apply one or more resolution enhancement technique (RETs) such as optical and process correction (OPC) that compensate for expected optical distortions that occur during the photolithographic process. One source of error that can be mitigated but not eliminated are long range intensity variations such as flare from the photolithographic printing system itself. Flare is caused by the scattering of illumination light due to defects or contamination on the lenses of the printing system. The effects of flare on an integrated circuit layout are typically inversely proportional to the number of features to be printed in a given area. That is, as the features to be printed in an area of an integrated circuit become more and more dense, the effects of flare are decreased. While it is not possible to eliminate flare, differences in flare intensity across the surface of an integrated circuit create processing variations. Increased flare in a given region generally increases the overall illumination in that portion of the integrated circuit, which affects the critical dimension or the smallest feature that can be printed on a semiconductor wafer.
While flare cannot be eliminated from the photolithographic printing system, it is desirable to have a mechanism for compensating for flare variations such that each region of the integrated circuit is processed similarly.